Memory devices, such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices are in common use in a wide variety of electronic systems, such as personal computers. Memory devices include one or more arrays of memory cells, which, in DRAM devices, are small capacitors that are arranged in rows and columns. A portion of a conventional DRAM memory array 10 is shown in FIG. 1. The array 10 includes a pair of complementary digit lines DL, DL*for each column of the array 10, only one pair of which is shown in FIG. 1. A large number of memory cells 12 are coupled to the digit lines DL, DL*. Each of the memory cells 12 includes an access transistor 16 and a memory cell capacitor 18 coupled between the transistor 16 and a cell plate 20, which is generally biased at one-half the supply voltage, i.e., VCC/2. The capacitor 18 generally stores a voltage equal to either the supply voltage VCC or ground. A gate of each access transistor 16 is coupled to a respective word line WL0, WL1, although only two of these word lines are shown in FIG. 1. For a “folded digit line” architecture, the even-numbered word lines, e.g., WL0, are coupled to the digit lines DL, and the odd-numbered word lines, e.g., WL1, are coupled to the complementary digit lines DL*. Thus, one word line WL is provided for each row of memory cells 12 in the array 10.
Each pair of digit lines DL, DL* is coupled to a respective sense amplifier 30 that performs two functions; first, “equilibrating” the digit lines and, second, sensing a differential voltage developed between the digit lines DL, DL* and then driving the digit lines to corresponding logic levels. Equilibrating the digit lines DL, DL*, which causes them to be at the same voltage, is accomplished using an equilibration circuit 34. The equilibration circuit 34 includes an equilibration transistor 36 coupled between the digit lines DL, DL*, and a pair of equilibration bias transistors 40, 42 coupled between one-half the supply voltage, i.e., VCC/2, and respective digit lines DL, DL*.
In operation, in response to an active high equilibration EQ signal, the equilibration transistor 36 turns ON to couple the digit lines DL, DL* to each other, and the equilibration bias transistors 40, 42 turn ON to couple the digit lines DL, DL* to VCC/2. As a result, after an equilibration period, the voltage on both of the digit lines DL, DL* is VCC/2, and the differential voltage between the digit lines is therefore zero.
As mentioned above, the sense amplifier 30 also performs the function of sensing a differential voltage developed between the digit lines DL, DL* and then driving the digit lines to corresponding logic levels. This second function is accomplished by an NSENSE amplifier 50 and a PSENSE amplifier 52. The NSENSE amplifier 50 includes a pair of cross-coupled NMOS transistors 56, 58, and the PSENSE amplifier 52 similarly includes a pair of cross-coupled PMOS transistors 60, 62.
In operation, the digit lines DL, DL*are initially equilibrated by driving the EQ signal active high for the equilibration period. After the differential voltage between the digit lines DL, DL* has reached substantially zero volts, the EQ signal transitions inactive low to turn OFF the transistors 36, 40, 42. One of the word lines is then driven active high to turn ON the access transistor 16 to which it is coupled. The ON access transistor 16 then couples a memory cell capacitor 18 to the digit line DL or DL* to which the access transistor 16 is coupled. This voltage from the capacitor 18 causes the voltage on the digit line DL or DL* to either increase slightly (if the capacitor 18 was at VCC) or decrease slightly (if the capacitor 18 was at ground).
A SENSE ENABLE line is then driven to a relatively low voltage, such as ground or a slight negative voltage, and an ACT line is driven to a relatively high voltage, such as VCC or a voltage elevated slightly above VCC. Assuming, for example, the voltage on the digit line DL has increased, the NMOS transistor 58 will turn ON to an extent that is greater than the amount the NMOS transistor 56 turns ON because the gate-to-source voltage of the transistor 58 will be greater. The complementary digit line DL* is therefore pulled toward the low voltage on the SENSE ENABLE line to a greater extent than the DL is pulled toward zero voltage. In a manner similar to the operation of the NSENSE amplifier 50, when the ACT line is driven high, the PMOS transistor 60 in the PSENSE amplifier 52 turns ON to an extent that is greater than the extent that the PMOS transistor 62 is turned ON because the gate-to-source voltage of the transistor 60 is larger. Therefore, the transistor 60 more strongly drives the digit line DL to VCC. Thereafter, the voltage on the digit line DL further increases and the voltage on the complementary digit line DL* further decreases, thereby causing the transistor 60 to drive the digit line DL more strongly, and the transistor 62 to drive the complimentary digit line less strongly, to the relatively high ACT voltage. At the same time, the increased voltage on the digit line DL and the decreased voltage on the complementary digit line DL* causes the transistor 58 to drive the complementary digit line DL* more strongly, and the transistor 56 to drive the digit line DL less strongly, to the relatively low SENSE ENABLE voltage. At the end of a sensing period, the NSENSE amplifier 50 has driven the complementary digit line DL* to the relatively low SENSE ENABLE voltage, and the PSENSE amplifier 52 has driven in the digit line DL to the relatively high ACT voltage. A COLUMN SELECT signal then transitions high to turn ON input/output (“I/O”) transistors 70, 72, thereby coupling the digit lines DL, DL* to respective complementary I/O lines 76, 78 in order to read a data bit from the array 10.
The sense amplifier 30 shown in FIG. 1 can also be used to read data bits from a memory array (not shown) having an open digit line architecture in essentially the same manner as explained above with reference to the folded digit line architecture shown in FIG. 1.
Although the sense amplifier 30 shown in FIG. 1 has performed well in the past, it is less able to quickly sense a differential voltage between the digit lines DL, DL* as the magnitude of the supply voltage VCC continues to decrease and transistor threshold voltages VT continues to decrease less rapidly, which is the trend for newer memory designs. Although the sense amplifier 30 may still correctly sense the voltage differential between the digit lines DL, DL*, the time required for the sense amplifier 30 to do so can increase to unacceptable levels.
There is therefore a need for a sense amplifier that can quickly sense a voltage differential between complementary digit lines even for a supply voltage having a relatively small magnitude.